Integrity and Reliability of Integrated CircuitS (IRIS), Phase III


DARPA is soliciting research proposals for a comprehensive exploration of the effects of extreme physical stresses on wear-out and aging mechanisms in CMOS FETs at 28nm and/or 14nm lithography node. The objective of the IRIS Program Phase III is to explore aging effects in both transistors and transistor interconnects to create predictive models and to test how precisely and rapidly specific wear-out mechanisms can be asserted, for the purposes of accelerating burn-in, aging, and wear-out. See the full DARPA-BAA-15-47 document attached.

General information about this opportunity
Last Known Status
Deleted 03/04/2016 (Archived.)
Program Number
Federal Agency/Office
Agency: Department of Defense
Type(s) of Assistance Offered
Cooperative Agreement, Grant, Other, Procurement Contract
What is the process for applying and being award this assistance?
Other Assistance Considerations
Formula and Matching Requirements
This program does not have cost sharing or matching requirements.
Who do I contact about this opportunity?
Headquarters Office
Mr. Kerry Bernstein
Program Manager
Website Address
E-mail Address
Financial Information


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